UCC27519DBVR SOT23-5 4A/4A single-channel high-speed low-side gate driver chip

Description

Specifications:
description:
UCC27518 and UCC27519 single-channel high-speed low-side gate driver devices can effectively drive metal oxide semiconductor field effect transistors (MOSFET) and insulated gate bipolar transistor (IGBT) power switches. The design scheme adopted by UCC27518 and UCC27519 can minimize the breakdown current, thereby providing a higher peak current source/sink pulse for capacitive loads, while providing rail-to-rail drive capability and ultra-short propagation delay (typical value is 17ns).
When VDD = 12V, UCC27518 and UCC27519 can provide 4A peak sink/source (symmetrical drive) current drive capability.
UCC27518 and UCC27519 have a wide VDD range of 4.5V to 18V, and a wide temperature range of –40°C to 140°C. When the VDD operating range is exceeded, the internal undervoltage lockout (UVLO) circuit on the VDD pin can keep the output low. The device can not only work at a low voltage below 5V, but also has the best switching characteristics in its class, so it is very suitable for driving new wideband gap power switching devices such as GaN power semiconductor devices.
The input pin thresholds of UCC27518 and UCC27519 are based on CMOS logic circuits, where the threshold voltage is a function of the VDD supply voltage. The typical upper input threshold (VIN-H) is 55% of VDD, and the typical lower input threshold (VIN-L) is 39% of VDD. The wide hysteresis between the upper and lower thresholds (usually 16% of VDD) provides excellent noise immunity and enables users to use an RC circuit between the input pulse width modulation (PWM) signal and the INx pin of the device Introduce delay.
UCC27518 and UCC27519 also have a unique enable function that can be left floating on the EN pin. Putting the EN pin in the unconnected state can realize the pin compatibility between UCC27518, UCC27519 and TPS2828, TPS2829 respectively. The voltage threshold of the EN pin is fixed and will not change with the bias voltage of the VDD pin. The typical upper limit of the enable threshold (VEN-H) is 2.1V, and the typical lower limit of the enable threshold (VEN-L) is 1.25V.
feature:
Low-cost gate driver, a high-quality alternative to NPN and PNP discrete solutions
Pin compatible with TI's TPS2828 and TPS2829 devices
4A peak source current and 4A peak sink current symmetrical drive
Fast propagation delay (typical value 17ns)
Fast rise and fall times (8ns and 7ns typical)
4.5V to 18V single supply range
The output remains low during VDD under-voltage lockout (UVLO) (to ensure glitch-free operation during power-up and power-off)
CMOS input logic threshold (function of supply voltage with hysteresis)
Hysteresis logic threshold for high noise immunity
EN pin for enabling function (not connected)
When the input pin is floating, the output remains at low level
The absolute maximum voltage level of the input pin is not limited by the bias supply voltage of the VDD pin
-40°C to 140°C operating temperature range
5-pin DBV package (Small Outline Transistor Package (SOT)-23)
parameter:
Number of channels (#) 1
Power switch MOSFET, IGBT, GaNFET
Peak output current (A) 4
Input VCC (Min) (V) 4.5
Input VCC (Max) (V) 18
Features Enable Pin
Operating temperature range (C) -40 to 140
Approx. price (US$)
1ku | 0.23
Rise time (ns) 8
Fall time (ns) 7
Prop delay (ns) 17
Input threshold CMOS
Channel input logic Non-Inverting
Input negative voltage (V) 0
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